mt48lc4m32b2参数资料 下载

简介：

mt48lc4m32b2参数资料为http://www.dianzi6.com整理发布，类型为芯片设计，本站还有更多关于芯片设计资料下载，芯片设计的资料。
正文：mt48lc4m32b2参数资料MT48LC4M32B2TG_MICRON

GENERAL DESCRIPTION
 The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. Accesses begin with the registra- tion of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits regis- tered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0¨CA11 select the row). The addres bits registered coincident with the READ or WRITE com- mand are used to select the starting column location for the burst access.
如果觉得《mt48lc4m32b2参数资料》不错，可以推荐给好友哦。