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正文： 该MC14015B双4陇Cbit静态移位寄存器建造的智慧 马鞍山P陇Cchannel和N陇Cchannel增强型器件 单片结构。它由两个相同的，独立 4陇Cstate串行陇Cinput /平行陇Coutput登记。每个注册 独立的时钟和复位输入，一个单一的串行数据输入。 国家登记册D型主陇Cslave倒装陇Cflops 。数据转移 从一个阶段到下一个在积极陇Cgoing时钟过渡 每个注册的时候可以清除高水平的基础上采用的是重 线。这些补充的MOS移位寄存器找到主要使用在 缓冲存储器和串行陇首席技术官陇Cparallel转换低战俘 耗散和/或抗噪声性能是理想的。
 二极管保护所有投入
 电源电压范围= 3.0直流电压至18日直流电压

 逻辑边陇CClocked倒装陇CFlop设计 逻辑状态是无限期保留或者时钟水平过高或过低; 资料转移到输出只有在积极的去 边缘的时钟脉冲。
 能够驱动双低陇Cpower的TTL负载或一低陇Cpow 肖特基的TTL负载的额定温度范围内工作。 The MC14015B dual 4¤Cbit static shift register is constructed wit MOS P¤Cchannel and N¤Cchannel enhancement mode devices in single monolithic structure. It consists of two identical, independent 4¤Cstate serial¤Cinput/parallel¤Coutput registers. Each register independent Clock and Reset inputs with a single serial Data input. The register states are type D master¤Cslave flip¤Cflops. Data is shift from one stage to the next during the positive¤Cgoing clock transition Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial¤Cto¤Cparallel conversion where low pow dissipation and/or noise immunity is desired. ? Diode Protection on All Inputs ? Supply Voltage Range = 3.0 Vdc to 18 Vdc ? Logic Edge¤CClocked Flip¤CFlop Design Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse. ? Capable of Driving Two Low¤Cpower TTL Loads or One Low¤Cpow Schottky TTL Load Over the Rated Temperature Range.
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