Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers 下载

This application note discusses the effects of powersupply
noise interference on PLL-based clock
generators. It describes several measurement
techniques for evaluating the resulting DJ
(deterministic jitter). Relationships are derived
outlining how frequency-domain spur measurements
can be used to evaluate timing jitter behavior.
Laboratory bench-test results are used to compare
the approaches, and demonstrate how to reliably
assess the PSNR (power-supply noise rejection)
performance of a reference clock generator.
Index Terms
DJ (deterministic jitter); TIE (time interval error);
PLL (phase locked loop); PSNR (power-supply
noise rejection); PSI (power supply interference); SJ
(sinusoidal jitter)
1. Introduction
Low-jitter clock generation is the core timing
component in network equipment. As the serial link
rate continuously grows to meet the ever-increasing
bandwidth demand, timing jitter becomes a
significant percentage of the data bit period. The
overall jitter budget in a system can be classified
into two parts: random jitter and DJ. The random
jitter contribution of a clock generator is usually well
defined, and can be translated into a peak-to-peak
value for a given bit-error-rate threshold. However,
the DJ caused by the periodic PSI is often a major
concern for system design, due both to the existence
of the on-board switching supply and to the highspeed
digital switching circuits inside ASICs.